This amplifies the difference between two inputs Vp and Vn the low impedance of this configuration is a drawback, but can be used in analog computing. Optimum VCC VDD can be +12/-12. AC signals common to Vp and Vn are canceled by this configuration.
Use a capacitor like 10nF plastic from pin 2 to 3 or across R2 to make circuit stable. For AC applications use LF351 TLO71 as they have good slew rate and also are FET inputs. For AC applications use a capacitor (1uF) in series with Ri to block DC Components. The Inputs have asymmetrical input impedance this affects CMRR, also use 1% tolerance MFR resistors for Rf and Ri.