A sample and hold is like an analog memory. If The digital control A is low 4066 switch is open, and when A is high switch is closed. U2B is a buffer so as to ensure quick charging of C1 thru 4066 on resistance of 100E.

Simple Sample and Hold with CD4066

U2A is a FET input opamp buffer which does not load or drain the cap C1. When A goes high the input analog sample is stored in C1. A has to be high for say 10*1uF*100E = 1mS, so that a proper stable sample is stored. When A is low C1 undergoes very slow discharge as opamp input resistance and 4066 off resistance is in giga ohms. The accuracy of reading Vout falls with respect to time due to leakage currents.

 
Sample and Hold with Standby CD4053

A, B, and C are the Digital Control for x, y and z input and output pairs.The voltage at Vinx is stored in C1 when A goes high, when A is low the voltage stored in C1 is read by buffer U2A. The stby or standby input should be low when sample and hold is operating. If stby is taken high then C1 Cap is isolated and leakage is minimum. The supply of +/- 7.5V is chosen as OFF resistance of 4053 is high at this supply.

 
Digital gain control of Opamp.

The gain of U1 can be controlled by a digital binary 1248 nibble at ABC. The gain at digital 000 is unity or 1 and the gain at various stages are set by 4051. There are eight different gains as the steps of gain resistor network is chosen by 4051. The on resistance of 4051 channel around 100E gets added to U1 pin 2 internal impedance. You can use separate resistor networks with trimpots for each channel if you require but keep the networks total burden on U1 pin 6 to around 10K, not less than than. You can use Read More …

 
Linearizing Circuit for Thermocouples

This circuit changes the gain of opamp U1B in four steps or segments. It can be used to get a linear output from most transducers to 1% levels.U1A is a amplifying buffer use it to boost the signal to the required level. The resistor values i have put are for an imaginary transducer, you have to design them. The buffered input signal is compared to reference switching points by LM339. LM339 changes the gain resistors of U1B thru the mux switch 4066. JP1 to JP4 can select either amplification or attenuation of signal. The resistor switched by 4066 can be Read More …

 
PLL using 4046 - Phase Locked Loop

CD4046 is a PLL or phase lock loop, it mainly consists of a VCO and phase comparators. This is a component in FM demodulation and modulation. It is used in a closed loop control to maintain a stable frequency. The Circuit above is good for learning the full use of a small Dual Trace Scope. The Circuit has both Analog and Digital areas and is a part of communication. Phase-Locked Loop Tutorial, PLL Phase Locked Loop: PLL Tutorial on Digital Phase-Locked Loops Phase Locked Loop Basics Read the pages above for building more Knowledge on PLL

 
AD590 based Temperature Sensor

The voltage at the point 1 of R4 will be :Vo=( 1+ ( 10K/22K)) * Vref = 3.63V as nominal Vref is 2.5V.AD590 is a current source which gives 1 uA / kelvin, It is independent of the voltage across the device. you can treat it like a current source or sink or impedance. total voltage across AD590 is 5V as opamp pin 2 is at virtual ground. This is the way you try to understand the design. The AD590, here is a constant current sink as cathode goes to -5. The current it sucks away or drains from node Read More …

 
Thermocouple Amplifier Standard

The OP07 is a low offset 75uV opamp, here it is used to amplify the output of a Thermocouple, the gain of this stage is high. The zeners are to protect any high voltage at input zapping the opamp. The Resistor R6 limits the current. The zeners should be low leakage or use clamping pull-up and pull-down diodes to +5 and -5 respectively. The RC low-pass filter formed by R6 and C2 reduce the mains hum or 50 Hz pickup of long thermocouple cables laid close to high current heater wiring. R1 is a offset null use or add if Read More …

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